1. Technical Field
The present invention relates to an interconnective substrate having a solder mask layer, e.g., a substrate in a semiconductor package.
2. Related Art
Certain types of conventional semiconductor packages, such as ball grid array (BGA) packages, include an internal substrate having top and bottom surfaces. The substrate includes a core insulative sheet, and a patterned layer of metal on each of the top and bottom surfaces. The patterned metal layer on the top surface of the insulative sheet includes a central rectangular chip pad and a plurality of metal circuit patterns radiating from the die pad. Each of the circuit patterns includes an inner bond finger adjacent to the die pad. The patterned metal layer on the opposite bottom surface of the insulative sheet also includes a plurality of metal circuit patterns, each of which terminates at a round land. Metal-lined vias extend vertically through the substrate and electrically connect the metal traces on the top and bottom surfaces of the sheet. A layer of an epoxy-based photoimageable solder mask material is applied over the top and bottom metal layers. The bond fingers, lands, and chip pad are exposed through chemically etched openings in the solder mask. A semiconductor chip is attached to the chip pad. A plurality of bond wires electrically connect each of the bond pads of the chip to respective ones of the bond fingers. A body of a hardened insulative molded encapsulant material covers the chip and the bond wires, and all or part of the top surface of the substrate. Solder balls may be fused to the lands of the bottom surface of the substrate. The solder balls, therefore, are electrically connected to the chip through the metal traces, vias, and bond wires.
The solder mask material is an insulative photoimageable epoxy-based material. A portion of the composition solder mask material, e.g., about 10 percent of the solder mask material, consists of acrylates and photoinitiators that allow the solder mask material to be patterned by photolithography. The solder mask is applied over the entire area of the top and bottom surfaces of the substrate, including over the respective layers of patterned metal, i.e., over the chip pad and current patterns. Subsequently, the solder mask material is hardened by curing. After curing, the top and bottom layers of the photoimageable solder mask material are respectively exposed to light through a silver halide contact mask that includes apertures corresponding to the locations of the chip pad and bond fingers for the top metal layer, and the lands for the bottom metal layer. Subsequently, a chemical development solution is applied, and the portions of the photoimageable solder mask that were not exposed to light through the apertures of the mask, i.e., the chip pad, bond fingers, and lands, are removed. Accordingly, the die pad, bond fingers, and lands are exposed through the etched apertures of the solder mask so as to be accessible the subsequent steps of chip attachment, bond wiring, and solder ball attachment.
A drawback of the photoimageable solder mask used in the above conventional process is that it is brittle due to the presence of the acrylates and photoinitiators. These materials are necessary, however, to enable the mask to be patterned by photolithography. Because the solder mask material is brittle, the solder mask material tends to crack when it is subjected to thermal stresses associated with the encapsulation process and operation of the chip in the package. Such cracks can lead to moisture penetration of the package and delamination of the solder mask from the encapsulant. Hence, conventional photoimageable solder mask materials can lead to failure of the package.
The present invention includes an interconnective substrate and methods of making such a substrate, wherein an outer surface of the substrate includes a layer of an insulative solder mask material over selected portions of a plurality of conductive (e.g., metal) circuit patterns. In one application, the substrate may be used to make a semiconductor package for housing a semiconductor chip, e.g., a ball grid array package or a land grid array package. Alternatively, a circuit board upon which a semiconductor package is mounted (e.g., a mother board in a personal computer) may be made formed by the methods of the present invention.
An exemplary method of making such an interconnective substrate includes providing an insulative sheet including a plurality of first circuit patterns on a first surface thereof. A layer of an insulative nonphotoimageable solder mask material is applied over the first circuit patterns. A plurality of apertures are formed through the nonphotoimageable solder mask layer using a laser so as to expose a selected region of at least some of the first circuit patterns. The exposed portion of the first circuit pattern may subsequently be electrically connected, through a bond wire or a solder ball, to an input/output terminal of a semiconductor chip that is mounted on the substrate or of a package mounted on the substrate.
The present invention is best understood by reference to the following detailed description when read in conjunction with the accompanying drawings.